Whole-project indexing, semantic navigation, linting, seamless waveform viewer integration, and an integrated schematic viewer, built for large ASIC and FPGA codebases.
Fromco indexes your SystemVerilog and Verilog codebase to provide fast semantic navigation across large RTL and verification projects, with instant cross-file resolution after any change or Git checkout.
Visualize module hierarchies and structural relationships directly from your RTL.
Expand and collapse submodules, highlight datapaths, and inspect signal propagation across complex ASIC designs.
Connect simulation results directly to your source code. Analyze signal values inline and navigate between waveform and source seamlessly.
Improve SystemVerilog code quality with semantic lint checks tailored for design and verification workflows.

Fromco implements the Language Server Protocol (LSP) and works with any LSP-compatible editor. Dedicated plugins for Visual Studio Code and Neovim simplify setup, while additional integrations can be built via a documented API.

Full feature access for evaluation. No limitations, one-day license.
Full access for individual engineers. Suitable for commercial and non-commercial use.
per month
Full access for individual engineers. Suitable for commercial and non-commercial use.
per month
Team licensing with custom terms, technical support, and optional consulting.
per year per seat
Self-serve plans accept major credit and debit cards viaPaddle. Enterprise customers may request invoice-based billing or wire transfers.
Yes. Early access, Personal and Enterprise plans allow commercial use. The Enterprise plan additionally provides team-oriented licensing options.
The Personal plan is intended for individual engineers. The Enterprise plan includes team licensing, technical support, consulting options, and floating license management.
An internet connection is required for license validation. Long offline periods are supported.
Still have questions about licensing or integrations?